SPEC Seal of Reviewal OMPL2001 Result
Copyright © 1999-2007 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 595 (1900 MHz, 64 CPU)
SPECompLpeak2001 = 672757       
SPECompLbase2001 = 620741       
SPEC license # HPG0005 Tested by: IBM Test site: Austin, TX Test date: Jan-2005 Hardware Avail: Nov-2005 Software Avail: Dec-2004
Benchmark Reference
Time
Base
Runtime
Base
Ratio
Peak
Runtime
Peak
Ratio
Graph Scale
311.wupwise_l 9200 168    875814        168    875814        311.wupwise_l base result bar (875814)
311.wupwise_l peak result bar (875814)
313.swim_l 12500 307    652359        275    726223        313.swim_l base result bar (652359)
313.swim_l peak result bar (726223)
315.mgrid_l 13500 415    521055        415    521055        315.mgrid_l base result bar (521055)
315.mgrid_l peak result bar (521055)
317.applu_l 13500 265    816109        243    889842        317.applu_l base result bar (816109)
317.applu_l peak result bar (889842)
321.equake_l 13000 797    261113        797    261113        321.equake_l base result bar (261113)
321.equake_l peak result bar (261113)
325.apsi_l 10500 330    509199        330    509199        325.apsi_l base result bar (509199)
325.apsi_l peak result bar (509199)
327.gafort_l 11000 272    646229        272    646229        327.gafort_l base result bar (646229)
327.gafort_l peak result bar (646229)
329.fma3d_l 23500 752    499790        752    499790        329.fma3d_l base result bar (499790)
329.fma3d_l peak result bar (499790)
331.art_l 25000 305    1311513         179    2229235         331.art_l base result bar (1311513)
331.art_l peak result bar (2229235)
SPECompLbase2001 620741         
  SPECompLpeak2001 672757         

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 595 (1900 MHz, 64 CPU)
CPU: POWER5
CPU MHz: 1900
FPU: Integrated
CPU(s) enabled: 64 cores, 32 chips, 2 cores/chip (SMT on)
CPU(s) orderable: 16,24,32,40,48,56,64
Primary Cache: 64KBI+32KBD (on chip)
Secondary Cache: 1920KB unified (on chip)
L3 Cache: 36MB unified (off-chip)/chip, 4 chips/MCM, 8 MCM/SUT
Other Cache: None
Memory: 256 GB DDR2
Disk Subsystem: 2x36GB SCSI, 15K RPM
Other Hardware: None
Software
OpenMP Threads: 128
Parallel: OpenMP
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
XL Fortran Enterprise Edition V9.1 for AIX
Other Software: ESSL for AIX V4.2
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information
Tested by IBM
 
 Portability Flags & Environment Variables
   -qfixed used in: 311.wupwise_l, 313.swim_l, 315.mgrid_l, 317.applu_l, 325.apsi_l
   -qfixed=80 used in: 319.galgel_l
   -qsuffix=f=f90 used in: 319.galgel_l, 327.gafort_l, 329.fma3d_l
 
 Base Flags
   C:       -q64 -O5 -qalign=natural -lmass -qsmp=omp
   FORTRAN: -q64 -O5 -lmass -qsmp=omp
 
 Base & Peak User Environment:
   OMP_NUM_THREADS=128
   OMP_DYNAMIC=FALSE
   XLSMPOPTS=SPINS=0:YIELDS=0:STACK=8000000:SCHEDULE=STATIC:STARTPROC=0:STRIDE=1
   MALLOCMULTIHEAP=1
   MEMORY_AFFINITY=MCM
 
 Peak Flags:
   -qsmp=omp used in all cases
   311.wupwise_l:    basepeak=1
   313.swim_l:       -q64 -O3 -qarch=pwr3 -qtune=pwr3
   315.mgrid_l:      basepeak=1
                     XLSMPOPTS=SPINS=0:YIELDS=0:STACK=8000000:SCHEDULE=STATIC:STARTPROC=0:STRIDE=2
                     OMP_NUM_THREADS=64
   317.applu_l:      -q64 -O3 -qarch=pwr4 -qtune=pwr4
                     XLSMPOPTS=SPINS=0:YIELDS=0:STACK=8000000:SCHEDULE=STATIC:STARTPROC=0:STRIDE=2
                     OMP_NUM_THREADS=64
   319.galgel_l:     -q64 -O5 -qhot=arraypad -qipa=noobject -qipa=partition=large -qmaxmem=-1
   321.equake_l:     basepeak=1
                     XLSMPOPTS=SPINS=0:YIELDS=0:STACK=8000000:SCHEDULE=STATIC:STARTPROC=0:STRIDE=2
                     OMP_NUM_THREADS=64
   325.apsi_l:       basepeak=1
   327.gafort_l:     basepeak=1
   329.fma3d_l:      basepeak=1
   331.art_l:        -q64 -O5 -qalign=natural -lmass -blpdata
                     EXTRA_CFLAGS= -DINTS_PER_CACHELINE=32 -DDBLS_PER_CACHELINE=16
 
 
  Alternate sources:
     Add critical region around update of linked list in parallel loop.
     Required src.alt available as ompm-purdue1-20040324.tar.gz
     Used for 331.art_l, base and peak.

  APAR IY62267 was applied to AIX 5L V5.3 to achieve Mantainence Level 1.

  SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
        the simultaneous execution of multiple thread contexts within a single processor
        core. (Enabled by default)
  MCM: Acronym for "Multi-Chip Module" (four dual-core processor chips + four L3-cache chips)
  ESSL: Engineering and Scientific Subroutine Library
  SUT: Acronym for "System Under Test"

  C:          IBM XL C for AIX invoked as xlc_r
  Fortran 90: IBM XL Fortran for AIX invoked as xlf90_r

  ulimits set to unlimited.
  Large page mode and memory affinity were set as follows:
     vmo -r -o lgpg_regions=4096 -o lgpg_size=16777216 -o memory_affinity=1
     chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
     shutdown -r




For questions about this result, please contact the tester.
For other inquiries, please contact [email protected]
Copyright © 1999-2007 Standard Performance Evaluation Corporation

First published at SPEC.org on 03-Mar-2005

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