SPEC CPU2006 Software OS and BIOS tuning Descriptions Bull Intel-based systems applications
- Hardware Prefetch:
-
This BIOS option allows the enabling/disabling of a processor mechanism
to prefetch data into the cache according to a pattern-recognition algorithm
In some cases, setting this option to Disabled may improve performance.
Users should only disable this option after performing application benchmarking
to verify improved performance in their environment.
- Adjacent Sector Prefetch:
-
This BIOS option allows the enabling/disabling of a processor mechanism
to fetch the adjacent cache line within a 128-byte sector that contains the
data needed due to a cache line miss.
In some cases, setting this option to Disabled may improve performance.
Users should only disable this option after performing application benchmarking
to verify improved performance in their environment.
- High Bandwidth:
- Enabling this option allows the chipset to defer memory transactions and
process them out of order for optimal performance.
- Power C-States:
- Enabling the CPU States causes the CPU to enter a low-power mode when the CPU is idle.
- Turbo Boost:
-
This BIOS option can be set to Power Optimized or Traditional. When Power
Optimized is selected, Intel Turbo Boost Technology engages after Performance state
P0 is sustained for longer than two seconds. When Traditional is selected, Intel
Turbo Boost Technology is engaged even for P0 requests less than two seconds.
- Demand Scrub:
-
Demand scrub occurs when the memory controller reads memory for data or
instructions and the demand scrubbing logic detects a correctable error. Correct
data is forwarded to the memory controller and written to memory. With demand
scrubbing disabled, the data being read into the memory controller will be corrected
by the ECC logic but no write to main memory occurs. Since the data is not corrected
in memory, subsequent reads to the same will need to be corrected.
- Max Numa nodes per module:
-
This option allows to confiure the number of proximity domains in a Module.
By default this value is set to 2.
Setting this value to 4 allows to get one Numa node per Intel socket
- Hemisphere Mode:
-
Hemisphere mode is a kind of socket level interleaving.
Hemisphere mode combines the tracking resources of both memory controllers within each processor for a more aggressive cache line pipelining.
When set, hemisphere mode reduces memory latencies.