SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2005 Standard Performance Evaluation Corporation
IBM Corporation
IBM System p5 505 (1650 MHz, 2 CPU)
SPECint_rate2000 = 34.1  
SPECint_rate_base2000 = 33.5  
SPEC license # 11 Tested by: IBM Test date: Sep-2005 Hardware Avail: Oct-2005 Software Avail: Oct-2005
Graph Scale Benchmark Base
Copies		 Base
Runtime		 Base
Ratio		 Copies Runtime Ratio
164.gzip base result bar (23.2)
164.gzip peak result bar (23.3)		 164.gzip 4 280    23.2   4 279    23.3  
175.vpr base result bar (27.2)
175.vpr peak result bar (27.0)		 175.vpr 4 239    27.2   4 241    27.0  
176.gcc base result bar (37.3)
176.gcc peak result bar (37.3)		 176.gcc 4 137    37.3   4 137    37.3  
181.mcf base result bar (47.4)
181.mcf peak result bar (48.2)		 181.mcf 4 176    47.4   4 173    48.2  
186.crafty base result bar (26.2)
186.crafty peak result bar (26.2)		 186.crafty 4 177    26.2   4 177    26.2  
197.parser base result bar (32.1)
197.parser peak result bar (32.5)		 197.parser 4 260    32.1   4 257    32.5  
252.eon base result bar (39.1)
252.eon peak result bar (39.8)		 252.eon 4 154    39.1   4 152    39.8  
253.perlbmk base result bar (26.5)
253.perlbmk peak result bar (28.9)		 253.perlbmk 4 315    26.5   4 289    28.9  
254.gap base result bar (33.0)
254.gap peak result bar (32.8)		 254.gap 4 155    33.0   4 156    32.8  
255.vortex base result bar (54.5)
255.vortex peak result bar (58.2)		 255.vortex 4 162    54.5   4 151    58.2  
256.bzip2 base result bar (35.6)
256.bzip2 peak result bar (36.7)		 256.bzip2 4 195    35.6   4 190    36.7  
300.twolf base result bar (32.2)
300.twolf peak result bar (32.2)		 300.twolf 4 432    32.2   4 432    32.2  
  SPECint_rate_base2000 33.5    
  SPECint_rate2000 34.1  

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM System p5 505 (1650 MHz, 2 CPU)
CPU: POWER5
CPU MHz: 1650
FPU: Integrated
CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip (SMT on)
CPU(s) orderable: 2
Parallel: None
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off-chip)/DCM, 1 DCM/SUT
Other Cache: None
Memory: 8x2GB
Disk Subsystem: 1x73GB SCSI, 15K RPM
Other Hardware: None
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 8.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information 
  Portability Flags:
    176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
    186.crafty:   -DAIX
    252.eon:      srcalt=fmax_errno
    253.perlbmk:  -DSPEC_CPU2000_AIX
    254.gap:      -DSYS_IS_BSD -DSYS_STRING_H
                  -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
    300.twolf:    -DHAVE_SIGNED_CHAR
 
  Base Optimization Flags:
    C:    -qpdf1/pdf2
          -O5 -blpdata -D_ILS_MACROS
    C++:  -qpdf1/pdf2
          -O5 -lhmu -qalign=natural
 
  Peak Optimization Flags
    164.gzip:     -qpdf1/pdf2
                  -O5 -qalign=natural -lhmu -blpdata -qfdpr -Q
                  fdpr -q -O3
    175.vpr:      -qpdf1/pdf2
                  -O5 -lhmu -blpdata -D_ILS_MACROS
    176.gcc:      basepeak=1
    181.mcf:      -O5 -blpdata -qfdpr
                  fdpr -q -O3
    186.crafty:   basepeak=1
    197.parser:   -qpdf1/pdf2
                  -O5 -blpdata -D_ILS_MACROS
    252.eon:      -qpdf1/pdf2
                  -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -D_ILS_MACROS
    253.perlbmk:  -qpdf1/pdf2
                  -O5 -lhmu -qalign=natural -blpdata -D_ILS_MACROS
    254.gap:      -qpdf1/pdf2
                  -O5 -qalign=natural -lhmu -blpdata -qfdpr -Q
                  fdpr -q -O3
    255.vortex:   -qpdf1/pdf2
                  -O5 -lhmu -blpdata
    256.bzip2:    -O5 -blpdata -qfdpr -D_ILS_MACROS
                  fdpr -q -O3
    300.twolf:    basepeak=1
 
 
  Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
  was used with 252.eon for POSIX-compatibility.

  The installed OS level is AIX 5L for POWER version 5.3 with the 5300-03 Recommended Maintenance package.

  SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
        the simultaneous execution of multiple thread contexts within a single processor
        core. (Enabled by default)
  DCM:  Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
  SUT:  Acronym for "System Under Test"

  Extended C:     IBM XL C for AIX invoked as cc
  ANSI C89:       IBM XL C for AIX invoked as xlc
  C++:            IBM XL C for AIX invoked as xlC

  ulimits set to unlimited.
  Large page mode and memory affinity were set as follows:
      vmo -r -o lgpg_regions=400 -o lgpg_size=16777216
      chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
      reboot -q
      export MEMORY_AFFINITY=MCM

  The following config-file entry was used to assign each benchmark process to a core:
       submit = let "MYCPU=2*\$SPECUSERNUM"; if (("\$MYCPU > 3")) then let "MYCPU-=3"; fi; bindprocessor \$\$ \$MYCPU; $command
  The "bindprocessor" AIX command binds a process to a CPU core.

  Use flags-description file IBM-20050919-AIX.txt.

For questions about this result, please contact the tester.
For other inquiries, please contact [email protected]
Copyright © 1999-2005 Standard Performance Evaluation Corporation

First published at SPEC.org on 18-Oct-2005

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