SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2005 Standard Performance Evaluation Corporation
IBM Corporation
IBM System p5 505 (1650 MHz, 1 CPU)
SPECint2000 = 1297     
SPECint_base2000 = 1259     
SPEC license # 11 Tested by: IBM Test date: Sep-2005 Hardware Avail: Oct-2005 Software Avail: Oct-2005
Benchmark Reference
Time		 Base
Runtime		 Base
Ratio		 Runtime Ratio Graph Scale
164.gzip 1400 187    747     187    747     164.gzip base result bar (747)
164.gzip peak result bar (747)
175.vpr 1400 136    1029      136    1026      175.vpr base result bar (1029)
175.vpr peak result bar (1026)
176.gcc 1100 79.8  1378      79.8  1378      176.gcc base result bar (1378)
176.gcc peak result bar (1378)
181.mcf 1800 71.7  2512      65.1  2763      181.mcf base result bar (2512)
181.mcf peak result bar (2763)
186.crafty 1000 98.4  1016      98.4  1016      186.crafty base result bar (1016)
186.crafty peak result bar (1016)
197.parser 1800 160    1123      160    1122      197.parser base result bar (1123)
197.parser peak result bar (1122)
252.eon 1300 92.6  1404      91.1  1428      252.eon base result bar (1404)
252.eon peak result bar (1428)
253.perlbmk 1800 198    910     180    1000     253.perlbmk base result bar (910)
253.perlbmk peak result bar (1000)
254.gap 1100 94.9  1159      94.9  1159      254.gap base result bar (1159)
254.gap peak result bar (1159)
255.vortex 1900 89.3  2129      83.3  2282      255.vortex base result bar (2129)
255.vortex peak result bar (2282)
256.bzip2 1500 127    1179      122    1232      256.bzip2 base result bar (1179)
256.bzip2 peak result bar (1232)
300.twolf 3000 213    1407      206    1457      300.twolf base result bar (1407)
300.twolf peak result bar (1457)
SPECint_base2000 1259       
  SPECint2000 1297       

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM System p5 505 (1650 MHz, 1 CPU)
CPU: POWER5
CPU MHz: 1650
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 2 cores/chip (SMT off)
CPU(s) orderable: 2
Parallel: None
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off-chip)/DCM, 1 DCM/SUT
Other Cache: None
Memory: 8x2GB
Disk Subsystem: 1x73GB SCSI, 15K RPM
Other Hardware: None
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 8.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information 
  Portability Flags:
    176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
    186.crafty:   -DAIX
    252.eon:      srcalt=fmax_errno
    253.perlbmk:  -DSPEC_CPU2000_AIX
    254.gap:      -DSYS_IS_BSD -DSYS_STRING_H
                  -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
    300.twolf:    -DHAVE_SIGNED_CHAR
 
  Base Optimization Flags:
    C:    -qpdf1/pdf2
          -O5 -blpdata -D_ILS_MACROS
    C++:  -qpdf1/pdf2
          -O5 -lhmu -qalign=natural
 
  Peak Optimization Flags
    164.gzip:     basepeak=1
    175.vpr:      -qpdf1/pdf2
                  -O5 -lhmu -blpdata -D_ILS_MACROS
    176.gcc:      basepeak=1
    181.mcf:      -O5 -blpdata -qfdpr
                  fdpr -q -O3
    186.crafty:   basepeak=1
    197.parser:   -qpdf1/pdf2
                  -O5 -blpdata -D_ILS_MACROS
    252.eon:      -qpdf1/pdf2
                  -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -D_ILS_MACROS
    253.perlbmk:  -qpdf1/pdf2
                  -O5 -lhmu -qalign=natural -blpdata -D_ILS_MACROS
    254.gap:      basepeak=1
    255.vortex:   -qpdf1/pdf2
                  -O5 -lhmu -blpdata
    256.bzip2:    -O5 -blpdata -qfdpr -D_ILS_MACROS
                  fdpr -q -O3
    300.twolf:    -O5 -blpdata -qfdpr -D_ILS_MACROS
                  fdpr -q -O3
 
 
  Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
  was used with 252.eon for POSIX-compatibility.

  The installed OS level is AIX 5L for POWER version 5.3 with the 5300-03 Recommended Maintenance package.

  SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
        the simultaneous execution of multiple thread contexts within a single processor
        core. (Enabled by default)
  DCM:  Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
  SUT:  Acronym for "System Under Test"

  Extended C:     IBM XL C for AIX invoked as cc
  ANSI C89:       IBM XL C for AIX invoked as xlc
  C++:            IBM XL C for AIX invoked as xlC

  ulimits set to unlimited.
  Large page mode and memory affinity were set as follows:
      vmo -r -o lgpg_regions=400 -o lgpg_size=16777216
      chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
      reboot -q
      export MEMORY_AFFINITY=MCM

  The following config-file entry was used to assign each benchmark process to a core:
       submit = let "MYCPU=2*\$SPECUSERNUM"; if (("\$MYCPU > 3")) then let "MYCPU-=3"; fi; bindprocessor \$\$ \$MYCPU; $command
  The "bindprocessor" AIX command binds a process to a CPU core.
  One core was deconfigured and SMT disabled at the open-firmware prompt, using the
  command
              boot -s cpu=1 -s smt_off

  Use flags-description file IBM-20051013-AIX.txt.

For questions about this result, please contact the tester.
For other inquiries, please contact [email protected]
Copyright © 1999-2005 Standard Performance Evaluation Corporation

First published at SPEC.org on 18-Oct-2005

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