SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2005 Standard Performance Evaluation Corporation
Hewlett-Packard Company
ProLiant ML570 G3 (3.0GHz, Intel dual-core Xeon)
SPECint2000 = 1360     
SPECint_base2000 = 1353     
SPEC license # 3 Tested by: Hewlett-Packard Company Test date: Sep-2005 Hardware Avail: Oct-2005 Software Avail: Jun-2005
Benchmark Reference
Time
Base
Runtime
Base
Ratio
Runtime Ratio Graph Scale
164.gzip 1400 141    990     141    990     164.gzip base result bar (990)
164.gzip peak result bar (990)
175.vpr 1400 159    880     155    905     175.vpr base result bar (880)
175.vpr peak result bar (905)
176.gcc 1100 66.6  1651      66.6  1651      176.gcc base result bar (1651)
176.gcc peak result bar (1651)
181.mcf 1800 137    1309      137    1310      181.mcf base result bar (1309)
181.mcf peak result bar (1310)
186.crafty 1000 91.2  1096      91.3  1095      186.crafty base result bar (1096)
186.crafty peak result bar (1095)
197.parser 1800 153    1179      152    1183      197.parser base result bar (1179)
197.parser peak result bar (1183)
252.eon 1300 69.5  1869      68.9  1886      252.eon base result bar (1869)
252.eon peak result bar (1886)
253.perlbmk 1800 105    1712      104    1725      253.perlbmk base result bar (1712)
253.perlbmk peak result bar (1725)
254.gap 1100 75.8  1451      74.6  1474      254.gap base result bar (1451)
254.gap peak result bar (1474)
255.vortex 1900 84.8  2240      84.8  2240      255.vortex base result bar (2240)
255.vortex peak result bar (2240)
256.bzip2 1500 154    975     154    974     256.bzip2 base result bar (975)
256.bzip2 peak result bar (974)
300.twolf 3000 197    1524      197    1524      300.twolf base result bar (1524)
300.twolf peak result bar (1524)
SPECint_base2000 1353       
  SPECint2000 1360       

Hardware
Hardware Vendor: Hewlett-Packard Company
Model Name: ProLiant ML570 G3 (3.0GHz, Intel dual-core Xeon)
CPU: Intel dual-core Xeon (3.0GHz, 2x2MB L2, 667MHz bus)
CPU MHz: 3000
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 2 cores/chip (Hyper-Threading Technology disabled)
CPU(s) orderable: 1,2,4
Parallel: No
Primary Cache: 12K micro-ops I + 16KBD (on chip) per core
Secondary Cache: 2048KB(I+D) (on chip) per core
L3 Cache: N/A
Other Cache: N/A
Memory: 16x1024MB PC2-3200
Disk Subsystem: 1x36.4GB 15K Ultra320 SCSI
Other Hardware:
Software
Operating System: Windows Server 2003 Enterprise SP1
Compiler: Intel C++ Compiler for 32-bit applications,
(Version 9.0 Build 20050624Z)
Microsoft Visual Studio .NET 7.0.9466 (for libraries)
MicroQuill Smartheap Library 7.0
File System: NTFS
System State: Default
Notes / Tuning Information
 +FDO: PASS1=-Qprof_gen  PASS2=-Qprof_use

 Base tuning for C programs:   -fast         +FDO  ONESTEP=yes shlw32M.lib
 Base tuning for C++ programs: -fast -Qcxx_features +FDO  ONESTEP=yes
 Portability flags:
   176.gcc: -Dalloca=_alloca /F10000000 
   186.crafty: -DNT_i386
   253.perlbmk: -DSPEC_CPU2000_NTOS -DPERLDLL /MT
   254.gap: -DSYS_HAS_CALLOC_PROTO -DSYS_HAS_MALLOC_PROTO
 Peak tuning:
   164.gzip:     -fast               +FDO  ONESTEP=yes 
   175.vpr:      -fast               +FDO  ONESTEP=yes
   176.gcc:      basepeak = 1
   181.mcf:      -fast               +FDO  ONESTEP=yes shlw32M.lib
   186.crafty:   -fast -Oa           +FDO  ONESTEP=yes shlw32M.lib 
   197.parser:   -fast               +FDO  ONESTEP=yes
   252.eon:      -fast               +FDO
   253.perlbmk:  -fast -Oa           +FDO  ONESTEP=yes shlw32M.lib
   254.gap:      -fast               +FDO  ONESTEP=yes
   255.vortex:   -fast               +FDO  ONESTEP=yes shlw32M.lib
   256.bzip2:    -fast -Oa -Qunroll1 +FDO  ONESTEP=yes shlw32M.lib
   300.twolf:    -fast               +FDO              shlw32M.lib
 BIOS Configuration Notes
   Hyper-Threading Technology disabled
 Other Configuration Notes
   /NUMPROC=1 flag was added to boot.ini to invoke uniprocessor environment.


For questions about this result, please contact the tester.
For other inquiries, please contact [email protected]
Copyright © 1999-2005 Standard Performance Evaluation Corporation

First published at SPEC.org on 18-Oct-2005

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