SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 575 (1900 MHz, 8 CPU)
SPECint_rate2000 = 167    
SPECint_rate_base2000 = 159    
SPEC license # 11 Tested by: IBM Test date: Jan-2005 Hardware Avail: Feb-2005 Software Avail: Dec-2004
Graph Scale Benchmark Base
Copies		 Base
Runtime		 Base
Ratio		 Copies Runtime Ratio
164.gzip base result bar (114)
164.gzip peak result bar (117)		 164.gzip 16 229    114     16 223    117    
175.vpr base result bar (142)
175.vpr peak result bar (142)		 175.vpr 16 183    142     16 183    142    
176.gcc base result bar (175)
176.gcc peak result bar (176)		 176.gcc 16 117    175     16 116    176    
181.mcf base result bar (258)
181.mcf peak result bar (275)		 181.mcf 16 130    258     16 122    275    
186.crafty base result bar (119)
186.crafty peak result bar (158)		 186.crafty 16 155    119     16 117    158    
197.parser base result bar (149)
197.parser peak result bar (149)		 197.parser 16 224    149     16 225    149    
252.eon base result bar (190)
252.eon peak result bar (194)		 252.eon 16 127    190     16 125    194    
253.perlbmk base result bar (116)
253.perlbmk peak result bar (126)		 253.perlbmk 16 287    116     16 265    126    
254.gap base result bar (143)
254.gap peak result bar (149)		 254.gap 16 143    143     16 137    149    
255.vortex base result bar (229)
255.vortex peak result bar (245)		 255.vortex 16 154    229     16 144    245    
256.bzip2 base result bar (168)
256.bzip2 peak result bar (170)		 256.bzip2 16 165    168     16 164    170    
300.twolf base result bar (165)
300.twolf peak result bar (165)		 300.twolf 16 337    165     16 337    165    
  SPECint_rate_base2000 159      
  SPECint_rate2000 167    

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 575 (1900 MHz, 8 CPU)
CPU: POWER5
CPU MHz: 1900
FPU: Integrated
CPU(s) enabled: 8 cores, 8 chips, 1 core/chip (SMT on)
CPU(s) orderable: 8
Parallel: no
Primary Cache: 64KBI+32KBD (on chip)
Secondary Cache: 1920KB unified (on chip)
L3 Cache: 36MB unified (off-chip)/DCM, 8 DCM/SUT
Other Cache: None
Memory: 32 GB
Disk Subsystem: 2x36GB SCSI, 15K RPM
Other Hardware: None
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information 
 Portability Flags:
   176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
   186.crafty:   -DAIX
   252.eon:      srcalt=fmax_errno
                 -I.
   253.perlbmk:  -DSPEC_CPU2000_AIX
   254.gap:      -DSYS_IS_BSD -DSYS_STRING_H -DSYS_HAS_TIME_PROTO
                 -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
   300.twolf:    -DHAVE_SIGNED_CHAR

 Base Optimization Flags:
   C:    -qpdf1/pdf2
         -O5 -blpdata -D_ILS_MACROS
   C++:  -qpdf1/pdf2
         -O5 -lhmu -qalign=natural

 Peak Optimization Flags
   164.gzip:     -qpdf1/pdf2
                 fdpr -q -O3
                 -O5 -blpdata -qfdpr
   175.vpr:      -qpdf1/pdf2
                 -O5 -blpdata -qalign=natural -D_ILS_MACROS
   176.gcc:      -qpdf1/pdf2
                 -O5 -blpdata -D_ILS_MACROS
   181.mcf:      fdpr -q -O3
                 -O5 -blpdata -qfdpr
   186.crafty:   -qpdf1/pdf2
                 fdpr -q -O3
                 -O4 -q64 -qfdpr -qarch=pwr3 -qtune=pwr3
   197.parser:   -qpdf1/pdf2
                 -O5 -blpdata -qalign=natural -D_ILS_MACROS
   252.eon:      -qpdf1/pdf2
                 -O4 -qarch=auto -qtune=auto -qalign=natural -D_ILS_MACROS
   253.perlbmk:  -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -blpdata -D_ILS_MACROS
   254.gap:      -qpdf1/pdf2
                  -O5 -blpdata -qalign=natural -D_ILS_MACROS
   255.vortex:   -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -blpdata
   256.bzip2:    fdpr -q -O3
                 -O5 -blpdata -qfdpr -D_ILS_MACROS
   300.twolf:    basepeak=1

 Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
 was used with 252.eon for POSIX-compatibility.

 APAR IY62267 was applied to AIX 5L V5.3 to achieve Mantainence Level 1.

 SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
       the simultaneous execution of multiple thread contexts within a single processor
       core. (Enabled by default)
 DCM:  Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
       For the 575, only one core is active per chip.
 SUT:  Acronym for "System Under Test"

 ulimits set to unlimited.
 Large page mode and memory affinity were set as follows:
     vmo -r -o lgpg_regions=1664 -o lgpg_size=16777216 -o memory_affinity=1
     chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
     reboot -q
     export MEMORY_AFFINITY=MCM

 The following config-file entry was used to assign each benchmark process to a core:
      submit = let "MYCPU=2*\$SPECUSERNUM"; if (("\$MYCPU > 15")) then let "MYCPU-=15"; fi; bindprocessor \$\$ \$MYCPU; $command
 The "bindprocessor" AIX command binds a process to a CPU core.

For questions about this result, please contact the tester.
For other inquiries, please contact [email protected]
Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 22-Feb-2005

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